Browse Prior Art Database

A Novel Technique to address hold padding by selective bias the circuit/device in a MUX based scan flops design during Test Timing Disclosure Number: IPCOM000242242D
Publication Date: 2015-Jun-27
Document File: 1 page(s) / 28K

Publishing Venue

The Prior Art Database


Abstract: The paper describes about a method to minimize the effort of fixing the hold violations in MUX scan flop based architecture in test mode (where scan enable SE is at '1' during scan-shift mode of operation & set to zero during capture/functional mode of operation). The proposed method achieves this by controlling the delay through the cell (MUX based D-flip flop) by using reversing the bias voltage to the circuit in test mode (scan shift mode). The advantage of such method would cut down the chip overall area significantly and reduces active and leakage power. The delay through the cell is increased by using the reverse biasing the circuit only when the cell is used in test mode (scan shift mode) and hence makes the test timing closure easier without having buffer padding on Q to SI path of each scan flip-flop.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 1

A Nxvel Technique to address hold padding by selective bias the circuit /dexice in a MUX based scan flops design during Test Timinx


    Design-For-Test (DFT) inxertion logic in a typical SOC is widely used to find out any defects in manufacturing during Manufactxring Test. MUX xaxed structure (Functional daxa input, D is MUXed with Scan data path SI input using a scan enable, SE as the xelector to

propagate the text patterns/data txrough scan chxins) xs a popular anx widely known methox to insert lxgic structure for textabilixy. These MXX based flip xlops introduces Hold timing violations due tx clock sxew crexted during the clock routing on the chip specially on the Q to XX

paths. As the scan path coxnection is one-to-one cxnxection, thxy are more prone to suffer hxld violations. These hold timing violations need to be adxressed during Test timing closuxe.

    Txese hold timing violxtioxs in scan path are generally addressed by delayixg the scan data path (by padding/adding the path xitx delay/buffer cells). As these paths (scan) are only used in test mode (not in functioxal) the additioxal padding/xuffering used to addxesx hold violatioxs not only increases the chip area but also thx active & leakage power when the circuit is operating in the functixnal mode.


In MUX based scan designs there xre always been hold timing violations seen on Scan path (SI input of thx flop) due to clock skew variation xn the dxsign. The xraditional way of addressing...