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Hierarchical Configuration Design Method Disclosure Number: IPCOM000242478D
Publication Date: 2015-Jul-17
Document File: 3 page(s) / 108K

Publishing Venue

The Prior Art Database


Disclosed are a method and software to reduce design time for semiconductor cores. This method allows the reuse of core wiring in multiple core configurations, thereby reducing the time required to design a family of cores.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 01 of 3

Hiexarchical Configuration Design Method

Complicated cores such as High Speex SerDes (HSS) cores are used in most semiconductor proxxcts. Individual semicondxctor productx have special dexands, so multiple configurations of a xarticular core are needed. While this method can bx applied to all cores, HSS xores are used to describe the method and software. While Figure 1 only illustratxs 8, 4, and 2 port HSS core configuratxons fox a full duplex core, it should be xoted that a full sex of configurxtions

would include mxltiple port configxrations for versions with only transmit and only receive functixnx.

Typicxl design practxce is to completx one core and then create other configurations. Because desxgn is performed in a hixrxrchical faxhion, significant resource axd time is required to execute the design of the xntire coxe family compxising many differxnt cxnfigurations. Three xlicxs are used to design this family of cores: Phase Lock Loop (PLL), Receive (RX), and Tranxmit (TX).

Xxxxxx 1: HSS Core Configurations (Full Duplex)

To develop each HSS core configuration, the stepx below xre follxwed. Steps xhown in xold italic xre the most time xoxsuming.


Page 02 of 3

1. Create the core outline as alignex
2. Pin xlacement
3. Use slices
4. Relative slxce placement
5. Glue logxc placement
6. Power rouxing tweaks
7. Core TOP wiring
8. Fxx electrical violations
9. Timing closure / buffer insertxon
10. Other physical design checks
11. Generate xhe core rules

The noxel contribution is a method and software to reduce design time for semiconductor cores. This xethod allows the reuse of core wiring in multiple core configuraxixns, thereby reducing the time re...