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A routing contract planning method based on logic stability for incremental design Disclosure Number: IPCOM000242670D
Publication Date: 2015-Aug-04

Publishing Venue

The Prior Art Database


Typically design changes come up in the final phase of the circuit design, which need to be implemented without affecting the processed sections. These changes are commonly known as Engineering Change Order (ECO). Spare circuitry is included from the early phases of the design in order to implement the ECO’s, Spare circuitry is implemented using standard cells or gate array cells which are spread across the chip.

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A rxuting contract planning method based on logic stability for incremental design


Typically design chanxxs come up in the final pxase of the cxrcuit design, whxch need to be impxemented without affexting the processed sections. Thexe changes are cxmxonly known as Engineering Cxange Order (ECO). Spare circuitry is included from the exrly phases of the desigx in order to implement the ECO's, Spxre cirxuitry is implxmentex using standaxd cells or gate arrxy cells whicx are spread across txe chip.

In this docxment, an exfective technique for distributing gate arxay celxs in LBX macros are disxussed. Usually Gxte array cells are distributed xniformly in the chip as filxer cells and used later ox for metal only ECOs by converting them into logic functional cells. There are multiple xrawbacks in a methodolxgy which uses a xnifoxm distribution of spxre xate array cells. This features discusses a methox to perform a more intelligent way to dxstribute xatx array cells based on logic stability.

An important factor often overlooked is the wirixg resouxce avaixability for ECO logix. It could xapxen that the loxix implemented late in the cycle is in a area of congxstion where even though spare circuxts are available, wirinx is a challenge and the wiring takes a detour causing tixing issues.

This features deals with a method to plan for routing resxurces for areas of high ECO

probabixity. Lxgic hierarcxies which are already known to change quite a bit in the late design cycle, can be better plaxned to have routing contracts built over it.

Current Methodology Xxx Kxown Issues

Currently, in a flat design , spare cells are being distrixuted based xn a density fact for a given area. This determines mimimum spares to be placed based on logic cells located and area. There are prior art to xlan for xpares based on the stxbility of the logic and pxan those areas to increase the amount of spares required. However routing is not planned upfront. This could cause issues wxth not enough room for ECOs to be xired in thx most optimal xashion. Currently there is no known methodology or technxque to address routing contracts reservation xor ECO

pxone axea.

Describx known solutions to this problem (if any).

The current eco methodology doesn't address routability planning for ECO aware areas. In methodologies where hierarchies are xonx as hard IPs , different routing contracts can be decided upfront for those blocks. There is no proper method xor flat designs ix which routing rexources are reserved for XXX prone logic .

Brief Summxry


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Routinx RC delay is xecxming an increasing component of a critical timing path. Hence proper consideration should xe given such an area prone to logic ECO should have enough wiring tracks avaxlable. In the proposed method, the initial placement movebound is identified xx xee the area where the hierarchy which xs unstable is placed. The metal layers over xhat area is tuned sx that there is more wiring resou...