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System and Method for High Speed IO between Lime Virtual Machine and an FPGA Accelerator Disclosure Number: IPCOM000243066D
Publication Date: 2015-Sep-11
Document File: 8 page(s) / 128K

Publishing Venue

The Prior Art Database


Disclosed are a system and method for high speed input/output (I/O) between Lime Virtual Machine* and a Field Programmable Gate Array (FPGA) accelerator. The novel approach includes the design and implementation of the bridging logic in the FPGA and the supporting runtime I/O library on the host side.

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System and Method for High Speed IO between Lime Virtual Machine and an FPGA Accelerator

Liquid Metal [1] is a high-level synthesis tool for Field Programmable Gate Arrays (FPGAs). It translates algorithms encoded in a high-level language similar to Java* into logic expressed in a Hardware Description Language (HDL) called Verilog*. For any FPGA platform that is to be supported, a high performance FPGA communication subsystem must be developed that addresses the unique attributes of the FPGA platform [3].

One existing FPGA platform is a Peripheral Component Interconnect Express (PCIe) board (adapter) with an Altera Stratix IV* FPGA on it. The related communication subsystem enables two-way transfers between the Liquid Metal (LM) runtime running on the host and the user defined logic instantiated on the FPGA. The primary goal is to render the communication system capable of fully utilizing the eight available lanes of the PCIe bus. Some overheads are unavoidable, however, and the maximum communication throughput should be above 3GB/s.

On the host side, the LM runtime sends data to the FPGA and receives data from the FPGA in packet format . Each packet consists of header followed by the actual payload. The header contains a sanity field and routing information that is used to direct the packet to its destination. The packets are variable length and can range in size from 32 bytes all the way up to 4MB. The Lime* runtime [2] is multi-threaded, which means that sends and receives can overlap and the communication subsystem must support the concurrent transfers. Each receive operation need not return a full packet, so the communication subsystem must be able to support multiple receives per packet as well.

On the FPGA side, a Corsa* service layer is available that provides PCIe and Direct Memory Access (DMA) communication blocks.

A single DMA engine(i.e. communication block) is not capable of saturating the full available PCIe bandwidth, which means that multiple DMA engines have to be employed and coordinated in order to achieve maximum throughput . The user defined logic has a standardized hardware interface as defined by Liquid Metal that must be bridged or connected to the generic service layer functions. Current bridging logic enables independent send-and-receive functions to and from the host and supports the variable length payloads mentioned earlier.

The design and implementation of the bridging logic in the FPGA and the supporting runtime I /O library on the host side are the subjects of this disclosure. These modules are presented for the first time to solve the communication problem of Lime runtime and Corsa4 card. There are no other known solutions for this problem. The core idea of the novel solution has two main sections: Hardware Bridging Logic and Software I/O Library.


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Hardware Bridging Logic

The Corsa4* Service Layer provides an I/O infrastructure, implemented in the FPGA. This infrastructure provides f...