Assertion based methodology to perform timing analysis on a Region-of-Interest (RoI)
Publication Date: 2015-Oct-17
The IP.com Prior Art Database
Disclosed is a methodology that uses an assertion based approach to hide the non-region-of- interest and to perform timing analysis only on the region of interest in Large block designs, where the designer want to focus their timing on a region of the design. This gives the flexibility to modify the region-of-interest easily if needed, and reuse of existing assertions, parasitics and netlist instead of creating and managing a pruned version.
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Assertion based methodology to perform timing analysis on a Region -of-Interest (RoI)
In Large block designs, the designer usually would want to focus their optimization on a region of the design. For the different optimization he does for the region-of -interest, he would want to see signoff quality timing results without having to time the entire design. The proposed methodology uses an assertion based approach to hide the non-region-of-interest and to perform timing analysis only on the region of interest. This gives the flexibility to modify the region-of-interest easily if needed, and reuse of existing assertions, parasitics and netlist instead of creating and managing a pruned version
In the proposed solution (Fig 1) , the designer gives the cells/nets (or source/sink registers) in the region-of-interest (ROI) as input. If cellname/netname in ROI is given, then the cone through cell/net is traced and translated back as source/sink register names . This list is called ROI-register-list. If the source is a port, add it to ROI-port list
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If any sink register in the RoI-register-list is eligible for slack stealing, find the sink regsiters connected to the sink register and add that to the ROI-register-list. (Fig 2)
If any net in the ROI-source-sink path has coupling, Find the aggressor nets of these nets, find their source and sink register and add that to ROI register list
If high accuracy is needed, check if the nets-of-interest given by the designer is an aggressor to any other net. Find this victim net, and find its source and sink. If original timing reports are available, check the slack at the sink register. If the slack is less than a threshold ( say 10ps), expand this source sink path, and add them to ROI-register-list (Fig 3)
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Figure 4 explains ROI timing. For all the registers in the design which are not a part of ROI-register-list, apply don't care assertion to the latch clock pin.
If the latches are driven by Local Clock Block (LCB)s, find the LCBs driving ROI-register-list and add that as ROI-LCB list. For all the LCBs not in ROI-LCB list, apply don't care assertion to its clock pin and input pins. This is to avoid tests at the LCB input pins for the ones which we are not interested in ( HLDN vs GCKN)
If the latches are driven by clock trees, find the source clock driving ROI-register-list and add that as ROI-clk list. For all the clock sources not in ROI-clk list, apply don't care assertion to this pin. This is to avoid clock tree pw tests for the clock tree which is not driving our region-of-interest.
For all the ports in the design, which are not in ROI-port list, apply don't care assertion to those ports
For all sink registers in ROI-register list, apply don't care assertion to its output pin.
Perform regular-signoff timing and write reports.
1) Create a pruned netlist with the region of interest and perform timing
Differences: This metho...