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Signal Wiring Congestion and IR drop co-optimization Disclosure Number: IPCOM000243844D
Publication Date: 2015-Oct-20
Document File: 4 page(s) / 52K

Publishing Venue

The Prior Art Database


In physical design process of Microprocessor / SOC, during routing phase, available routing resources are intelligently used to physically connect all standard cells / hard and soft IP(s) present meeting desired design targets in terms of timing, power etc. If globally or locally within the chip, there is less supply of routing resource as compared to demand, that results in global or local congestion which can degrade timing and eventually leads to functional failure by creating "shorts" / "opens" etc. During, placement and routing process, there are many available and emerging techniques to take care of congestion issue essentially by tweaking placement and wiring options of different components. As we enter into LBS (Large Block Synthesis) paradigm, dealing with multi-million cells, we have a desperate need of explore techniques to optimally use available metal usage for power routing, clock routing & signal routing. Currently, there is no known utility which is context aware and does in-flight calculation to mitigate IR drop and congestion simultaneously. This articles provides a solution in this area where a joint cost function which does a hand-shake and valid trade-off for optimally use metal tracks for IR drop and congestion during routing.

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Page 01 of 4

Signal Wiring Congestion and IR drop co -optimization

In this proposal congestion driven track sharing between power and signal tracks in low & high switching areas. In case of low switching high congested area power tracks will be loaned to signal routing. In case of high switching less congested area signal tracks will be loaned to

power routing. At post routed stage congestion plot and IR/Switching plot will be analyzed simultaneously with proposed engine to achieve efficient balance between power and signal routing without affecting any QOR.

Proposed Algorithm

1) Build IR drop and Congestion map for each bin.

2) Check if congested region has significant presence of consecutive green bins of IR drop mapping around it.

3) If (2) is found satisfactory, then
4) Verify which metal layer has high congestion in the congested region.

5) Provide the metal tracks used from power distribution network for signal routing to solve congestion. Replace power straps or power trunks with power staples or power via.

6) Re-do (4) & (5) with these constraints enforced.

Concept illustration


Page 02 of 4

 This is an illustration of co-analysis of congestion and IR drop violation.

 It can then be used for re-allocation of routing tracks between power and signal.


IR Analysis

      - IR information for different metal levels of power grid. Congestion Analysis

- Horizontal vs Vertical

- Lower vs Upper metal layers

Before Start

- Divide the design in smaller tiles

- Find IR and Congestion metrics for each tile after initial power/signal routing ( Iteration 1 )

- Assign a Cost Factor (say K1) for Power routing based on signal congestion in each tile. ( Higher congestion ~ Higher K1)

      - This costs factor will be shared through a power contract for signal routing. When to start

- Power routing (Iteration 2) for given IR/Congestion profile.

• For each tile evaluate possible power routing templates ( a predefined style of power routing that can solve a give IR spec )

• Evaluate a self-Cost (say K2) for each power template based on metal resource required to implement it. (H...