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Work Queue FIFO With Intervention Data Disclosure Number: IPCOM000243866D
Publication Date: 2015-Oct-22
Document File: 3 page(s) / 46K

Publishing Venue

The Prior Art Database


Disclosed is an idea to use cache highest point of coherency (HPC)/cache inject techniques in combination with memory FIFO storage for improved performance. The proposed idea solves the initial FIFO latency start-up cost by utilizing cache HPC/inject techniques.

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Work Queue FIFO With Intervention Data

DMA engines (or, in general, any sort of hardware accelerator logic; i.e., cryptography, data compression) often use a work queue to manage work, frequently implemented as a first-in-first-out (FIFO) queue. In the prior art, this FIFO may be implemented inside of the DMA engine. Doing so allows reduced latency as the work queue element is written directly to the DMA engine/accelerator. The cost of such an approach is the amount of memory needed to hold the FIFO; the larger the FIFO, the more memory required to be held in the DMA engine (cost, power, etc.).

    An alternate prior art approach is to put the FIFO in system memory. This allows an arbitrarily large FIFO to exist, but comes at the expense of latency as a work element is first written to memory, the DMA engine is notified of the write to memory (i.e., by an interrupt, or in P9 by an ASB_Notify command), and then the work queue element is read from memory by the DMA engine. Of course, the DMA engine may implement prefetching of the FIFO elements (best of both worlds) but doing so does not prevent the latency associated with the first entry being fetched for the empty FIFO case.

    In this invention, the work queue FIFO is kept in memory, allowing for an arbitrarily large FIFO at minimal incremental cost. For steady state (non-empty) conditions, the DMA engine/accelerator simply reads elements from the FIFO in memory. If the DMA engine work queue is empty, the DMA engine/a...