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Method for Using a Cache to Improve Link Bandwidth Disclosure Number: IPCOM000244098D
Publication Date: 2015-Nov-09
Document File: 2 page(s) / 31K

Publishing Venue

The Prior Art Database


Described is a method of caching packet header information on both sides of a link in order to enable the sending side to not have to send the entirety of successive nearly-duplicate headers over the link, thus improving the efficiency of the link to provide more bandwidth for the actual data.

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Method for Using a Cache to Improve Link Bandwidth

In a succession of PowerPC* processors, various types of links were used to connect the chips of the system together to exchange commands, responses, data, etc., with each other in order to construct a Symmetric Multiprocessor System (SMP). In order to identify the content of what is on these links, a concept called a "frame" was used. A frame consists of a header, which identifies the frame type, and the header is followed by the content. In some embodiments, frames were always of a fixed size, and in others, frames were of variable sizes based on the type of frame. In all cases, a subset of the content was data headers and their accompanying data. Since these are computer systems with a defined cacheline size of 128 bytes, but with a minimum data transport granule of 16 or 32 bytes within the system fabric, it is not uncommon for a data packet crossing the link to have the same routing tag (which identifies the ultimate destination of the data) as a recent preceding data packet. Finding a way to not send a data header for every data packet can significantly boost the effective bandwidth of a link by shrinking the number of bytes needed to transmit a full cacheline by ~10%, depending on the frame formats.

    In some of the processors, a data package was always kept together to be sent over the link, with a "last transfer" indicator to tell the receiving end when to start looking for the next packet header. This limited the data header overhead on the link, but also put some restrictions on what the on-chip data arbiter was allowed to do, which led to some performance inefficiencies and bottlenecks.

    On other processors, a method called "gathering" was used to avoid forcing the central arbiter to keep cachelines intact through the network. When a data packet arrived at the link logic, a circuit would hang onto it for a few cycles and compare it to the next data to arrive before releasing the original packet out the link. If the next data packet had a matching data header, the first packet's data would have its "gather bit" turned on, which accomplished two things: 1) to tell the receiving side that the next packet coming was a match, and would not have a data header on the link, and 2) to wait for it to arrive before forwarding the aggregate onto the next place. The basic data frame on the link was 32 bytes, with a 4-byte data header. Thus, successful gathering of a 128-byte cacheline eliminates three data headers, leaving more link bandwidth for other content. The main problem with this method is the need to wait for following data to determine whether gathering can occur (latency increase), and if the following data doesn't arrive within the time window, or some other unrelated data arrives next, the opportunity to eliminate an unnecessary data header is lost.

    This invention takes advantage of the fact that when a cacheline is transported across the fabric, the 32-byte pieces tend...