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Method to Validate Return Address Prediction and Return Address Stack Corruption Recovery Mechanism in the Microprocessor

IP.com Disclosure Number: IPCOM000245453D
Publication Date: 2016-Mar-10
Document File: 4 page(s) / 57K

Publishing Venue

The IP.com Prior Art Database


Described is a methodology where one can create a speculative test pattern to stress the return address prediction and return address stack functionality. The methodology of creating this return address branch patterns is built over the basic speculative branch node creation algorithm.

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Method to Validate Return Address Prediction and Return Address Stack Corruption Recovery Mechanism in the Microprocessor

Modern superscalar speculative processors depend heavily on the branch prediction logic and every generation of processors improves the branch prediction logic. In the emerging workloads, one observes more of branch address prediction requirement. This address prediction plays a key role in the languages like C++, numerous scripting languages (which are current gaining lots of interest in the emerging workloads). Various performance studies carried out over numerous emerging workloads and software like Big Data, NoSQL, Python*, SPSS**, InfoSphere**, cloud suite, MineBench, etc. brings out the importance of branch prediction requirements for the next generation workloads.

    Due to the highly speculative nature of these emerging workloads, there has been a tremendous amount of improvement happening in improving the speculation design of the microprocessor. Link stack hardware plays a huge role in determining the function return address and predicts the same in the speculative execution. When the branch prediction (control flow prediction) goes wrong, there is a high possibility that the return address stack will get corrupted. There, recovery logic is one of the key logic incorporated into the processor micro-architecture to recover the mispredicted path in the link stack.

    This is one of the key features to be tested to cover the IFU log-in and branch prediction schemes. The invention of branch test-generation algorithm [*] addresses the direction prediction very effectively, but it still leaves some gap in addressing the effective test-generation approach for the return address prediction and recovery algorithm. This disclosure addresses the problem of effective test-generation for the link stack address prediction hardware by creating interesting test scenarios to stress any type of return address prediction hardware.

    The algorithm builds a set of instructions that are clearly delineated into a set of "nodes" where each "node" consists of a fixed number of instructions. The algorithm then interconnects the different nodes using a pseudo-random branch pattern generation methodology. The reference provides a detailed approach on how a basic test pattern can be generated. At the end of this build process, there is a set of nodes where each node has a taken path and a not-taken path. This path information is recorded in a Branch Information Structure. The self-modifying code generation module uses the "Branch Information Structure" to actually build a couple of branch instructions in each node for the taken and not-taken paths respectively. Each of these branches is built at fixed offsets from the start of a node.

    The limitation of the above algorithm is that every "node" has a pair of direct/indirect branch instructions (that transfer control to the taken or not-taken path) that always branch to a particular node i...