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Predictive address translation prefetch for units using an Address translation caching mechanism. Disclosure Number: IPCOM000245589D
Publication Date: 2016-Mar-21
Document File: 1 page(s) / 18K

Publishing Venue

The Prior Art Database


We describe a mechanism which allows translation logic working vs. A P9 nMMU to predict the address translations an AFU will require based on the translation requests outstanding. This mechanism allows for streamlined AFU performance in a CAPI system.

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Predictive address translation prefetch for units using an Address translation caching mechanism.

In P9 systems, a CAPI attached accelerator (AFU) must use a PSL (P Service Layer) in order to connect to the processor.

The PSL is used (among other things) to translates the AFU's Effective Addresses into Real Addresses used by the system.

The actual translation is not done by the PSL but rather by the nMMU (nest Memory

Management Unit) unit which sits in the processor itself.

Communications between the PSL and nMMU is done by special transactions called Checkout Requests and Responses. These are sent over the link connecting the PSL and the Processor (such as PCIe) and therefore have a high latency.

Each Checkout request can translate a single memory page address.

The translations are cached by the PSL, so that if the AFU requests multiple accesses to the same page there will be a high likely hood that PSL already holds the translation and will not need to send out another Checkout Request.

We propose a mechanism to predict that an AFU will require access to a consecutive page address and send out a Checkout Request before the AFU requests it, thus reducing AFU operation latency.

The PSL translation mechanism will implement a tracking algorithm which will predict when an AFU is accessing the same page in sequential order and will then send out a translation request for the next sequential page address.

The implementation of this invention is actually very simple.