A method to synchronize verification environment, logic interface and specification (Spec Coherenchy tool)
Publication Date: 2016-Aug-15
The IP.com Prior Art Database
The tool consists of the following components which interlock together: · VHDL parser ? check that each input/output has a specification description. For every signal in the top level design, create an entry in the database that will be used by the other components described below. · Facs Parser ? parse the facility files which connect the design interface to the verification environment. Update the database accordingly, creating VHDL, FACS pairs. · RTX parser ? parse the verification environment monitors and drivers. Check that each signal is constructed in an interface monitor and that each input is driven. · VhdlDoc tool - create an interface specification out of the VHDL top level. · HTML generator- generates an HTML page in a table format with a summary of the signals status. Each signal is checked for existence (design, verification environment and interface specification), width and direction (In/Out). Missing or mismatched signals are reported to the user.
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A method to synchronize verification environment , , (Spec Coherenchy tool
Spec Coherenchy tool )
One of the challenges in pre-silicon chip development is keeping hardware logic in sync with the verification environment when the logic specification dynamically changes throughout the development process. It often occurs that the owner of an interface document will miss updating the interface document due to an oversight or lack of communication with the logic designer who made the interface change. Keeping the interface document in sync with the hardware logic is crucial for maintaining the verification process throughout the project.
The Specification Coherency tool main purpose is to improve the synchronization between the Logic team and the Verification team, with respect to the interface signals (specification).
The tool generates a HTML report that summarizes all inputs/outputs in the design under test.
The report indicates for each signal if it exists in the logic and verification environment (which includes the interface, monitors and drivers), as defined in the specification. The report also indicates whether there are missing signals and where (interface document, verification environment and actual hardware logic). The report also indicates when a signal is not being driven by a driver or checked by a monitor.
logic interface and specification
logic interface and specification
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Motivation - Examples of logic, specification and verification not being in sync when adding a new signal to logic but not documenting the change in the specification and therefore the verification environment does not match the new addition:
Width of an existing bus is changed - in this case we might get a compilation error due to the mismatch of the bus width but we might also miss driving the additional bits .
Name of an existing signal is changed - this change is usually covered by compilation checks but still requires the verification environment person to find the source of the compilation fail which sometimes is a challenging task.
A new signal is added - this addition will not cause a compilation error and unless this signal is part of the main logic functionality (such as a valid bit or a clock), then this change might go unnoticed and therefore the functionality of this new signal will not be verified.
A new signal is added only on the driving unit but not on the receiving unit - usually a mismatch such as this will not be found at the unit verification level but at the multi -unit verification level since it requires both units to communicate and function in order to be found .
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The tool consists of the following components which interlock together:
6 VHDL parser - check that each input/output has a specification description. For every signal in the top level design, create an entry in the database that will be used by the other components descr...