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III V Nano Sheet Process Flow Disclosure Number: IPCOM000247368D
Publication Date: 2016-Aug-29
Document File: 6 page(s) / 46K

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The Prior Art Database


Disclosed are a structure and method to fabricate a iii v nanowire.

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III V Nano Sheet Process Flow

Nano wires offer improved electro statics, which is vital for next generation Complementary Metal Oxide Semiconductor (CMOS) scaling. Along with density advantages, the nano wire also has advantages with respect to performance.

The novel contribution is a structure and method to integrate III-V / SiGe lateral nanowires/sheets.

The following figures represent a heterogeneous nanosheet integration flow. This flow shows large area III-V + etch flow, but this can also be done with replacement fin. The sheet release and Replacement Metal Gate (RMG) module are unified. The order of epi, strips, and RMG can be switched.

Figure 1: Blanket Silicon Germanium (SiGe) on Silicon (Si), multiple repeats to form required number of GAA wire/sheet layers - end with sacrificial Si sheet (assuming SiGe channel - for Si channel, sacrificial sheet is SiGe).

Figure 2: Pattern pMOS block layer into dielectric

Figure 3: Etch trench for aspect ratio trapping (ART)

Aspect ratio needs to be 3:1 or so - if fin pitch is 20-40nm, implies min depth of ~200nm - there is likely a practical limit to how many fins/stacks can be formed.


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Figure 4: Deposit sidewall spacer material - needs to be nitride-like

Figure 5: Spacer etch

Etch can land on SiGe or Si or at various depths in the SRB/substrate.

Figure 6: III-V epi - grow sheet layers, end with InP
Could be some non-planarity at sheet edges, but can likely cut these during fin patterning. Alternatively,...