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Pin-Density Optimization of Integrated Pin-Fin Coolers for Power-Semiconductor Modules Disclosure Number: IPCOM000247610D
Publication Date: 2016-Sep-20
Document File: 7 page(s) / 342K

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The Prior Art Database

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Thomas Gradinger: AUTHOR [+2]


*Abstract: Power semiconductor module with a first side and a second side opposite the first side, with a copper layer on the first side, pin fins on the second side, and with semiconductor dies on the copper layer, where the copper layer has a segmentation to connect the semiconductor dies according to an electric circuit. The proposed solution of varying the pin density is cost neutral. It does not effect the manufacturing technology of the pin-fin cooler which is, for example, made from AlSiC. The difference in heat spreading among the dies compensated by varying the pin density, i.e. the number of pins per footprint area of the semiconductor module. Advantageously, close to a chip that sits on a small copper patch and has therefore poor heat spreading, pins are arranged more densely. Close to a chip that sits on a large copper patch and has therefore good heat spreading, a smaller pin density is chosen.

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Pin‐Density Optimization of Integrated Pin‐Fin Coolers for Power‐ Semiconductor Modules 

Authors: Th. Gradinger, D. Torresin, M. Habert


The present disclosure describes a new solution of cooling of power-semiconductor modules.


An efficient way of cooling power-semiconductor modules is by using pin fins and a water/glycol mixture as cooling fluid. In case of integrated cooling, the pin fins are part of the semiconductor module. The latter typically consists of a DBC (direct bonded copper) bonded to the cooler base plate. The DBC is a sandwich of a top copper layer, an insulating ceramic layer, and a bottom copper layer. The top copper layer is segmented to form electric connections and separations between the semiconductor dies according to a certain needed electric circuit. An example cross- section of a power-semiconductor module is shown in Figure 1.

Figure 1: Cross-section of a power-semiconductor module with DBC, with integrated pin-fin cooling. Thicknesses not to scale.

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If the cooler material is electrically insulating, then, in principle, the electric insulation of the DBC and the bottom copper layer can be omitted. An example is sketched in Figure 2.

Figure 2 Cross-section of a power-semiconductor module without DBC, with integrated pinfin cooling. Thicknesses not to scale.

The top copper layer plays an important role in spreading the heat generated by the semiconductor dies. This is so because of the good thermal conductivity of copper, and because the top copper layer is the layer closest to the dies. However, the segmentation of the top copper layer puts a limit to the effective heat spreading. Some dies sit on smaller patches of copper (formed by the segmentation), others sit on larger patches. The dies on larger patches get better heat spreading and stay cooler. It may also be that a die does not sit at the center of a copper patch, but rather close to an edge. This results in poor heat spreading in the direction towards the edge.

Temperature differences between dies are unwanted, since they lead to electrical asymmetries, increasing semiconductor stress and reducing performance and lifetime. In case of components with a negative temperature coefficient (NTC), even a thermal runaway may occur. In particular, the body diode in SiC semiconductors has an NTC. To achieve a uniform temperature distribution among the dies is therefore a goal of every semiconductor module design.

It is typically not possible - at least not without accepting other disadvantages - to change the segmentation of the top copper layer in such a way that all dies have the same heat spreading. The segmentation is dictated by various boundary conditions, such as

 the basic electric circuit (connections) of the dies;
 the need to minimize stray inductances;
 the need to limit current densities and copper losses;