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Coreless ETS with MIS and embedded passive components Disclosure Number: IPCOM000247974D
Publication Date: 2016-Oct-14
Document File: 6 page(s) / 184K

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The Prior Art Database

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Coreless ETS with MIS and embedded passive components


Semiconductor devices are widely used in modern electronic products. In the integrated circuit packaging systems, it is critical to reduce the manufacturing costs, of which the substrate is the biggest. In the conventional substrates, costly materials such as core and pre- preg and complicated processes are required.

The patent US 9171739 teaches a solution to use a coreless Embedded Trace Substrate (ETS) to replace the conventional substrates, with the advantages of good reliability due to preventing bump bridging; and the advantages of reduced costs due to adopting dual process and a coreless substrate. The patent also uses Molded Interconnect Substrate (MIS) to replace the conventional substrate materials. MIS uses Epoxy Mold Compound (EMC) to replace costly Laser Direct Structuring (LDS) material or polytetraflurorethylene pre- impregnated (PPG) lamination. Therefore, the combination of coreless ETS and MIS in the patent further reduces the substrate manufacturing costs and meanwhile improves reliability. The patent US 9305809 discloses a method to embed passive components to MIS with the advantages of freeing up extra space; and the advantages of simpler and cheaper assembly processes. However, a bridging risk of adjacent traces may exist in the patent manufacture in the process of solder print-passive attach-reflow, since there is no solder resist between adjacent traces. In addition, the conductive vias are higher than the trace layer as shown in Fig. 1. Thus it is difficult to attach passive components to the trace layer because of the non- flat surface of the substrate.

Fig. 1 The integrated circuit packaging system in the patent US 9305809


This invention discloses a method to embed passive components in coreless ETS and MIS with dry film functioning as solder resist to solve bridging issues of the adjacent traces in the passive attach process. In addition, the use of dry film, instead of molding compounds, allows a flat surface of the trace layer for passive components to attach to, which improves the efficiency of solder print process. Furthermore, this invention adopts a dual process, in which two identical substrates can be manufactured simultaneously.

The first embodiment of the subject invention is shown in Fig. 2 to Fig. 6. A carrier is prepared for manufacture of the integrated circuit packaging system in Fig. 2. The carrier can include a detach core in the centre and conductive foils in direct contact with top and bottom surfaces of the detach core. The conductive foils are made of conductive materials, such as

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Coreless ETS with MIS and embedded passive components

copper or alloy thereof; while the detach core is made of detachable materials which are easy to be detached from the conductive foils at the end of the manufacturing process. Then materials needed in the upcoming process are attached to the conductive foils, whic...