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Embedded IC for Molded Interconnect Substrate Disclosure Number: IPCOM000248049D
Publication Date: 2016-Oct-21
Document File: 4 page(s) / 412K

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Embedded IC for Molded Interconnect Substrate


The typical molded interconnect substrate, MIS, features the pre-molded copper filled strip evolving from the circuitry complexities of leadframe and laminate substrate. Figures 1A and 1B are representing the respective versions of one metal layer and dual metal layers MIS, which are commonly used as a bare substrate in the flip chip and BGA assembly.

Typical MIS Structures

Figure 1A: Original single metal layer MIS version

Figure 1B: Original dual metal layers MIS version

This inventionrelates to embedding an integrated circuit chip in the form of flip chip and wire bond chip to the Molded Interconnect Substrate. The MIS structure is inherently benefited from the fine pitch capability and I/O layout flexibility that is contributing on the ease to pre-assemble the chip or micro-chip inside the strip. The chip types such as ASIC and ASSP are some of possible IC chips that can be embodied with MIS. This concept is complementing to the original MIS, which enable to free up extra space for the design flexibility in the assembly house, thus, enhanced the overall package functional application.

Figure 2A: Single metal layer MIS with IC or micro-chip

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Embedded IC for Molded Interconnect Substrate

Figure 2B: Dual metal layers MIS with IC or micro-chip


The assembly process steps for MIS with chip is started with trace development depicted in Figure 3A, which resort to plating to create the first Cu metal layer onto the carrier, followed by forming the Cu via with an extended height, given the consideration of the chip attach structure thickness as shown in Figure 3B. A defined package active area, away from vias is subjected to the deposition of conductive metal elements such as Ni/Au to form the bonding pad, whereby flip chip is attached to it after the reflow and underfill processes as shown in Figure 3C. The premolding process in Figure 3D is performed, having the chip and Cu vias encapsulated in the dielectric layer which is formed by resin. The entire mold surface including the solder ball pad openings or terminal pads is then coated with thin Cu seed layer through plating to...