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ETS with Cu Recess Prohibits

IP.com Disclosure Number: IPCOM000248051D
Publication Date: 2016-Oct-21
Document File: 6 page(s) / 331K

Publishing Venue

The IP.com Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 6

ETS with Cu Recess Prohibits


The existing embedded trace substrate (ETS) design concept consists of the bump pad recess that is susceptible to the risk of insufficient contact area between pad and solder ball. The excessive recess depth inconsistency of the Cu pads could induce contactless occurrence during flipchip attach as shown in Figure 1, and the problem is exacerbated by the fine pitch application. The solution to the addressed problem is to stave off the recess depth of trace and bump pad, so it is at comparable level to the surface top in the substrate. The concept is to introduce metal element which is resistive to the etching chemical such as Au, Au Ni, Ni Pd Au, Tin, Tin alloy namely prohibits, whereby it is selectively applied and its coverage must be adequately wider than the target pad or trace, to ensure no exposure of underlying metal is the crux of the matter. The recess prohibits concepts cover the options either on trace or bump pads as shown in Figure 2A, or for both trace and bump pad as shown in Figure 2B. The respective concept process flow is described in the next section.

Figure 1: Existing ETS Design

Figure 2A: ETS with Cu Recess Prohibits on Bump Pads in 2D view

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ETS with Cu Recess Prohibits

Figure 2B: ETS with Cu Recess Prohibits on Both Trace and Bump Pads in 2D view


Figure 2A shows the embedded trace substrate (ETS) with Cu recess prohibits on bump pads. The process flow is started with the carrier preparation using a detachable core carrier made of either metal, organic or inorganic material. It can be an optional double-sided entity of same structure replicated single-sided processes as shown in Figure 3A.

Figure 3A: Carrier Preparation

Figure 3B: Selective Au Flash Plating

Figure 3C: Metal 1 Opening

The carrier surface is selectively deposited with Au flash such as Au/Ni for wire bond pad, represented by yellow colour in Figure 3B, which is considered the prohibit for the top surface of the bump pad and trace. The metal layer is formed, in which the opening of metal is corresponding with the Au flash, having the Au flash dimensions relatively wider as in overlapping condition for bump pads emphasized in Figure 3C, alternatively, the Au flash to be applied on the target trace area instead. Figure 3D shows the metal Cu plating for the openings is conducted or so called metal 1 is formed. Followed by process step in Figure 3E, whereby the defined area of metal is removed by DF stripping and has proceeded with prepreg or PPG lamination process.

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ETS with Cu Recess Prohibits

Figure 3D: Metal 1 Cu Plating

Figure 3E: DF Stripping and PPG Lamination

The laser or drilling to form vias through the prepreg layer is performed for the relevant bump pads. Next, the via fill and patterning processes are exerted accordingly to form the metal 2 as shown in re...