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# Method of Maximizing Frequency across Voltage and Frequency Space

IP.com Disclosure Number: IPCOM000248146D
Publication Date: 2016-Nov-01
Document File: 4 page(s) / 54K

## Publishing Venue

The IP.com Prior Art Database

## Abstract

Disclosed is a dynamic voltage frequency scaling tuning methodology in statistical static timing analysis (SSTA). The main concept is to replace a canonical clock assertion with a tuned value of frequency.

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Page 01 of 4

Method of Maximizing Frequency across Voltage and Frequency Space

Voltage (V) and frequency (F) are changed during chip and/or core operation to maintain the overall power budget for changing workloads. The typical process uses an adaptive voltage regulator. During design, an acceptable voltage range and 'nominal' frequency are typically known. During hardware disposition, the best voltage and frequency pairings can be selected for the design at hand.

However, design closure to only the 'nominal' targets leads to non-optimal timing at alternate V-F pairings (i.e., a few paths will limit the ability to adjust V and F). Optimal V-F pairings can be determined a priori with multiple timing corners and assertion sets and multiple trial-and-error iterations. This is a costly process in terms of resources and turn-around time. The voltage/frequency pairs follow a nonlinear path, making it difficult to assume a linear change in frequency with change in voltage.

Figure 1: Voltage/frequency space

The novel solution is a dynamic voltage frequency scaling tuning methodology in statistical static timing analysis (SSTA). The core novelty is the method to determine optimal voltage/frequency pairs from:

 Given voltage range

 Given single clock period at a V within the given range which must be closed to 0 slack (call this Vnom/Tnom)

 Solving for limits of Tcyc at limits of V, using iterative assertion of canonical clock

1

Page 02 of 4

The main concept is to replace a c...