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PoP using interposer adhesive with spacer Disclosure Number: IPCOM000248200D
Publication Date: 2016-Nov-09
Document File: 3 page(s) / 354K

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The Prior Art Database

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Page 01 of 3

PoP using interposer adhesive with spacer


Electronic products have become progressively more complex, the demand for enhanced functionality and smaller size has been driven. Although the benefits of enhanced functionality and smaller sizes are apparent, those make another problem. In particular, electronic products typically have to accommodate a high density of semiconductor devices in a limited space. One approach is to stack semiconductor device packages on top of one another to form a stacked package, which is also sometimes referred as a PoP (Package of Package). The upper package is typically electrically connected to lower semiconductor package with interconnection structure (top ball). The top balls are bonded to pads (top ball pad) on the lower semiconductor package.

Fig. 1 shows comparison of conventional PoP structure and our invention. The interposer is getting thinner to reduce height of a package. The thinner interposer leads warpage issue. The warped interposer collapses the top balls causing the failure such as short or open occurs. In addition, uniform gap between top interposer and bottom package is hard to control.

To solve the problems, an adhesive layer having spacers is formed over the semiconductor die. The adhesive holds top interposer to limit warpage and the included spacers sustain the regular offset between the interposer and the bottom package.


Page 02 of 3

PoP using interposer adhesive with spacer

Fig. 2 ~ 7 shows one embodiment of manufacturing process.

Fig. 2 shows top ball attach phase. A general wiring substrate (bottom substrate) is provided and top balls are disposed to bottom substrate. The top balls may include a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable material. For example, the top balls can include solder balls.

Fig. 3 shows flip chip assembly phase. A semiconductor chip is disposed on the bottom substrate adjacent to top ball and electrically connected to the bottom substrate.

Fig. 4 shows that molding material encapsulates the bottom package. The molding material is applied to the upper surface of bottom substrate so as to cover or encapsulate the top ball and semiconductor chip. Laser ablation or drilling is next carried out with respect to an upper surface of the molded structure.

Laser ablation is carried out with laser, which applies a laser beam to remove portion of the molded structure. In particular, the laser is positioned and substa...