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Cavity molded interconnect PoP manufacturing method for low warpage solution Disclosure Number: IPCOM000248220D
Publication Date: 2016-Nov-10
Document File: 5 page(s) / 590K

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Cavity molded interconnect PoP manufacturing method for low warpage solution


A common semiconductor device arrangement includes an upper semiconductor package stacked over a lower semiconductor package, i.e. package-on-package (PoP). The upper semiconductor package is typically electrically connected with a substrate. Recently a substrate having a cavity is emerged to reduced whole package height. But it has high warpage during stacking packages due to difference of substrate thickness from center to edge. It may cause irregular joints, bump crack, and poor yield.

Disclosed is manufacturing method of cavity molded interconnect PoP for low warpage. A carrier is provided. A cavity molded interconnect substrate (CMIS) is attached on the carrier. Top side of the bottom PoP is disposed on the CMIS. Reflow is performed and the top ball is attached on the pads of the substrate. During reflow, since the CMIS is securely attached on the carrier, the warpage is limited. Eventually, productivity is increased and failure is reduced.


Fig. 1 ~ Fig. 9 shows process flow of one embodiment.

As shown in Fig. 1, a carrier is provided. The carrier is preferably copper core laminate (CCL).

Fig. 2 shows forming a first trace layer. The photo-resist layer is disposed on the top surface of a carrier. For example, the photo-resist layer is a positive type. A photo mask with pattern design is disposed above the photo-resist layer such that the photo-resist layer is selectively exposed to the radiation. The exposed portion is removed in the developing process. A first trace layer is formed on the patterned openings. The first trace layer can be formed by

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Cavity molded interconnect PoP manufacturing method for low warpage solution

plating, and preferably has more than one layer, whose material is Cu, Ni, Au, or Sn. Afterwards, the patterned photo-resist layer is removed, and the first trace layer is retained on the carrier.

Afterward, Vertical connection is formed on the first trace layer. The forming vertical connection method includes the above steps of forming first trace layer, which are not repeatedly described in the following.

Fig. 3 shows forming a molding material layer having a cavity. A mold chase having a protrusion is used for forming a cavity on the molding material layer. A molding material layer is formed for covering the first trace layer and vertical interconnection. The material of the molding material layer may be an insulating material, and preferable epoxy molding compounds (EMC). The molding material layer may be thinned for exposing the upper surface of the vertical connection. Grinding is preferable.

Fig. 4 shows forming a seed layer phase. The seed layer is formed over molding material layer and vertical connection. Preferably, the seed layer is formed by electroless plating.

After that, in Fig. 5, the carrier and seed layer is removed. The manufacture of a CMIS is completed.

Fig. 6 shows attachi...