Power optimization methodology for combinational logic
Publication Date: 2016-Nov-17
The IP.com Prior Art Database
This paper describes a method for power optimization of standard cell digital logic designs. The method improves power consumption by substituting specified types of combinational cells (in identified sub-circuits) with similar cells that have an additional input. The method connects the additional input so that the replacement cell is placed in a lower power state for a portion of the time. When the sub-circuit operates in a normal manner the average power of the sub-circuit is reduced.
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Power optimization methodology for combinational logic Introduction
This paper describes a method for power optimization of standard cell digital logic designs. The method improves power consumption by substituting specified types of combinational cells (in identified sub- circuits) with similar cells that have an additional input. The method connects the additional input so that the replacement cell is placed in a lower power state for a portion of the time. When the sub- circuit operates in a normal manner the average power of the sub-circuit is reduced.
Background and Problems Solved
Commonly used power optimization schemes generally involve improving either leakage power or dynamic power but rarely (if ever) both at the same time. A common approach to leakage reduction is to replace identified cells with cells that are logically equivalent but which have one or more of the following modifications - shorter gate widths, longer gate lengths and higher thresholds. Each of these differences reduce the speed of the cell and this speed reduction limits the degree to which the method can be performed. Other power reduction schemes may require new cells to be developed or complicated biasing schemes to be implemented or are heavily dependent on the process technology. Existing schemes may limit performance or require extra processing steps, leading to reduced demand or increased product cost.
This new approach improves both leakage and dynamic power together without the usual normal requirements of new cells, extra processing steps, significant performance degradation, complicated biasing schemes etc. The new scheme can be applied to almost any standard cell logic design.
Improves the power consumption of a standard cell logic design by substituting certain combinational cells in identified sub-circuits with a similar family cells that have an additional input. Uses the additional input on the replacement cell to dynamically place the replacement cell in a lower power state when the output of the replacement cell (or original cell) has no effect on design operation, so that the average leakage and dynamic power of the sub-circuit is lower than the pre-optimized sub-circuit. Identifies cells to be replaced through a combination of cell functionality, sub-circuit functionality, sub- circuit connectivity, cell input state (high/low) information and cell state leakage information.
This method optimizes a standard cell digital logic design to improve power consumption. The technique changes (optimizes) the design to reduce power consumption while maintaining logical equivalence. This method might run faster and yield better results if it were integrated into Synthesis or
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a Place and Route tool. The method could also be implemented as a Tcl script but the best results require intensive compute power and so tool integration should provide a better solution.
This method does not require n...