Browse Prior Art Database

Low warpage solution for Stepped Laminate Interposer PoP Disclosure Number: IPCOM000248387D
Publication Date: 2016-Nov-23
Document File: 2 page(s) / 109K

Publishing Venue

The Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 59% of the total text.

Page 01 of 2

Low warpage solution for Stepped Laminate Interposer PoP


Various Package-on-package (PoP) structures have been developed for many applications, such as hand phones and other portable devices in which the circuit board space is limited. In the PoP structure, the top package is typically a memory package whereas the bottom package is a processor package. The PoP technology is more preferred to the stacked-die circuit technology, since different memory packages can be substituted in a PoP circuit. In addition, the top and bottom packages can be tested independently, which lowers down the manufacture cost.


The subject invention discloses a further improvement to a stepped laminate interposer PoP with half copper etching layer. In Fig.1, this invention includes a stepped laminate interposer PoP, solder openings at the center on the top side and half copper etching layer inside the cavity on the bottom side. The subject invention has the principle advantage of providing the best unit warpage (around 44um at room temperature), by matching the copper ratio in the top metal layer (M1 layer) with that in the bottom metal layer (M2 layer).

In Fig.1, the M1 layer contains large metal pads directly at the peripheries and several discrete small metal pads at the center. The large metal pads in the M1 layer are partially covered by solder resist, with the central portions exposed; while some small metal pads in the M1 layer at the center are uncovered an...