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Substrate having embedded pads for components Disclosure Number: IPCOM000248393D
Publication Date: 2016-Nov-24
Document File: 6 page(s) / 356K

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Substrate having embedded pads for components


Recently, a package that passive components attached on the bottom side of a substrate, this structure is defined as land side capacitor (LSC), has attracted considerable attention. But there is a problem that the passive component may be damaged because of low profile, which defines gap between top surface of a board and bottom surface of a component. Some factors such as warpage or handling may cause defect to the components.

To solve the problem, attachment pad for passive component is embedded in the substrate. Embedded pad leads increased profile, which is gap between top surface of board and bottom surface of component, so that the risk that the component contacts the board and get damage is reduced. Increased profile enables to use smaller solder ball, so that higher I/O is possible. The circuit pattern is formed by forming a trench on an insulation layer using a laser and then plating.


Fig. 2 ~ 12 shows a process of manufacturing one of embodiments.

Fig. 2 shows providing a carrier phase. A carrier is preferably copper core laminate (CCL).

Fig. 3 shows forming via hole phase. The via hole may be formed by drilling or laser drilling. As shown in Fig. 4, the via hole is filled with conductive material such as gold, silver, nickel, copper or the like. Afterward, the first conductive pattern layer is formed on upper and lower sides of a carrier. The first via is connected with parts of the first conductive pattern layer. After forming the first conductive pattern layer, as shows in Fig. 5, insulation layer is formed on the upper and lower sides of the carrier. Prepreg (PPG) is preferably laminated on the substrate.

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Substrate having embedded pads for components

In Fig. 6, a plurality of trenches for components pads and via holes are formed on insulation layer. The plurality of trenches is formed on the lower side of insulation layer using laser. Subsequently, via holes are formed by laser processing, drilling, or the like.

Afterward, as shown in Fig. 7, a plurality of trenches and the via holes are plated with conductive metal, preferably Cu. The plurality of trenches may be excessively plated with the conductive metal. The excessively plated portion may be additionally etched or grinded as shown in Fig. 8.

In one of embodiments, the plating can be conducted to via holes and trenches in sequence. For example, the via holes are masked by photoresist and then plating is conducted to trenches. After that, the photoresist on the via holes is removed and the trenches are masked by photoresist. The via holes are plated with conductive metal. The plating can be controlled, so that the optional process such as grinding or etching to flatten the excessively plated is not required.

Fig. 9 shows forming second conductive pattern layer. Photoresist for forming the second conductive pattern layer is disposed on both sides of the insulation layer. The photores...