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High IO use Center Hollow Interposer TSV Disclosure Number: IPCOM000248395D
Publication Date: 2016-Nov-24
Document File: 3 page(s) / 406K

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The Prior Art Database

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High IO use Center Hollow Interposer TSV


A common semiconductor device arrangement includes an upper semiconductor package stacked over a lower semiconductor package, i.e. package-on-package (PoP). The upper semiconductor package is typically electrically connected to the lower semiconductor package. It is well known that the consumers of the next generation electronic devices are demanding increased functions and features that are packed in a smaller size, consuming less power, and costing less than the earlier generation.


Disclosed is a PoP having a hollow interposer with through silicon via (TSV) semiconductor chip for stacking high I/O device for higher performance. A hollow interposer allows a semiconductor die to be placed inside of the interposer, so that the whole package height can be reduced. Also the interposer allows solder ball for interconnect top package instead of Cu post for increasing I/O, so that the manufacturing cost is lower. The semiconductor chip can include TSV, which can interconnect to top package together with the hollow interposer. The increased I/O can accept high I/O devices such as high densification memory. Eventually, electrical performance is improved.

Fig. 1 shows one of embodiments of disclosed package structure. A substrate for base of PoP is provided. The substrate is general laminate substrate to allow semiconductor chips for interconnecting with external device. A semiconductor chip is disposed on the substrate. The chip includes a bump, which can includes Cu, solder, Ni, Au, or combination thereof. The semiconductor chip includes TSV. The semiconductor chip is electrically connected to the substrate by the bump. A hollow interposer is disposed on the substrate. The hollow interposer is electrically connected to the substrate by top ball, which is preferably solder ball. The cavity of the hollow interposer matches position of the semiconductor chip, which is surrounded by the hollow interposer. Encapsulant covers over semiconductor chip and hollow interposer, where the top surface of the encapsulant is coplanar with the top surface of the

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High IO use Center...