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Method to verify complex hardware state machines with graph based test scenarios Disclosure Number: IPCOM000249110D
Publication Date: 2017-Feb-07
Document File: 4 page(s) / 71K

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The Prior Art Database


This article describes a method to build up a hardware verification graph that can be used to verify a complex hardware procedure which can be executed manually step by step or automatically by some hardware means

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Method to verify complex hardware state machines with graph based test scenarios

A method is disclosed to write a graph based verification code in a way that it can check a sequence, which can be executed manually or by an automated process , without code duplication.

A new approach in hardware verification is the use of so called graph based verification. Breker verification systems provides with Trek a tool to use this . In this particular environment a verification engineer can describe in a textual way a graph. This is used to control the verification flow to be executed in a valid sequence (e.g. first enable power before starting another operation ).

Trek uses the therm "goal" to describe an node within the graph. There are three types of goals :

1) Select goal. If traversing such an goal exactly one of its children is packed as next node. Probabilities for each path can be configured . Graphical notification uses a diamond to represent such a goal

2) Sequence goal. All children of this goal are executed in the given order . Graphical notification uses a square to represent such a goal , the children are connect be arrow. The sequence given by top to down order of the children .

3) Leaf goal. This goal has no children. The graphical representation uses a square.

Modern hardware setup often requires complex procedures to be executed before a device can be used. This is usually done by firmware or some other software means . This also provides flexibility to the system owner to configure the hardware to better suffer its needs. In addition these hardware often provides means to setup itself automatically by implementing one well checked configuration executed by a finite state machine. So the user can choose which way to go. A verification engineer has to check both approaches. So usually the implemented graph contains both ways (see Figure 1). That includes a lot of code duplication and maintenance .


Figure 1: State of the art graph based modelling

Figure 1 shows a state of the art graph for a so called IPL sequence . So the graph can select the manual or the automated process . If it chooses the manual way it applies each step sequentially. Each step is coded in one leaf goal which includes the appropriate checking code as well . In the auto process there are just 2 goals. One to trigger the hardware state machine and one that checks that the sequence is executed in the correct order.

The new approach uses some features pr...