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Restoring of Distributed History Buffer with Partial ECC Fields in A Multislice Microprocessor

IP.com Disclosure Number: IPCOM000250377D
Publication Date: 2017-Jul-06
Document File: 5 page(s) / 774K

Publishing Venue

The IP.com Prior Art Database


In a microprocessor, load instructions may access data that is unaligned and spread across multiple data-cache blocks. Each cache block may broadcast only a portion of the data back to the register file array as a ‘partial write’. When an entry in the History Buffer (HB) is partially written (that is, only some of the bytes are written, and the other bytes are waiting for real data to come in), and a flush occurs, then this entry must be restored to the Register File (RF). A writeback collision occurs if the other ‘partial write’ occurs during this recovery process, and interferes with the data written from the HB. Writeback collision detection and restore retry process can slow down the flush and restore of the History Buffer and reduces performance. This disclosure describes a process whereby the partially written data can be restored without waiting for the unused bytes to be written back to the HB due to restore and write back collision. In this disclosure, the ECC bits of partially written data can be restored according to the byte mask, and the partial data can be written into the RF along with the new ECC bits. This allows the un-used bytes to write into the general purpose register (GPR) independently of the restoring HB bytes.

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Restoring of Distributed History Buffer with Partial ECC Fields in A Multislice Microprocessor


Instructions in a microprocessor can execute and write their results to a multitude of destinations.

These destinations may include register mappers, issue queues, reservation stations, and history

buffers. Figure 1 shows an example processor, where instructions are fetched from the instruction

cache (I$), buffered and dispatched to execution slices. The Data Cache (DCache) is partitioned among

the execution slices, with a network allowing any execution slice to talk to any LSU DCache block.

Figure 1: Multislice processor

The DCache is partitioned into blocks that are Double Word (DW) aligned, with one block per execution

slice. Each DCache block can return Load data on a separate result bus. This allows load instructions to

issue from any execution slice and access any DCache block. When a Load access is unaligned and has to

access multiple DCache blocks, the Load Data will return from multiple LSU DCache blocks on multiple


result buses. Each result bus will have partial Load data. Figure 2 shows an unaligned load, requesting

data from two DCache blocks. Each DCache block broadcasts data back to all the execution slices.

Figure 2: LSU writeback

The LSU DCache blocks can return the partial data result busses at different times, thus each writeback

destination needs to be able to write each byte independently, rather than writing all 8-bytes at once. A

writeback byte-mask is broadcast from the LSU slices to the execution slices, and tells each location

which bytes are valid to be written. For the purposes of this disclosure, only array destinations are

considered, because arrays require ECC calculations. These arrays are located in the Mappers and the

History Buffers.

ECC generation:

ECC (error-correcting code) allows the processor to detect and correct single-bit errors in data from the

array. The ECC mechanism can correct single-bit errors and regenerate the data from a corrupted

memory cell. Multi-bit errors are detected and reported, but are uncorrectable.

Figure 3 shows ECC generating during array write. An ECC is generated on the data before it writes into

the array. When an entry is read from the array, the ECC value is also read out from the array. New ECC

is generated on the read-data and compared against the ECC value that was stored in the array. This

comparison indicates whether there was no error, a correctable (single-bit) error, or uncorrectable

(multi-bit) error in the array.

Figure 3: ECC generation during Array write


Flush Recovery:

When an entry in the History Buffer is partially written (that is, only some of the bytes are written

because the load spans multiple LSU slices), and a flush occurs, then this entry must be restored from

the history buffer to the register file. This causes a read operation in the history buffer array and a write

operation in the register file array. Since the data is only partially wri...