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Method and Structure of Forming VFET Bottom Spacer and Replacement Gate

IP.com Disclosure Number: IPCOM000250753D
Publication Date: 2017-Aug-30
Document File: 8 page(s) / 493K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a novel flow for forming the Vertical Field Effect Transistor (VFET) bottom spacer and replacement gate to improve the thickness control of the bottom spacer with a lower k-value. In addition, it provides full replacement gate flow for better gate stack control.

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Title Method and Structure of Forming VFET Bottom Spacer and Replacement Gate Abstract Disclosed is a novel flow for forming the Vertical Field Effect Transistor (VFET) bottom spacer and replacement gate to improve the thickness control of the bottom spacer with a lower k-value. In addition, it provides full replacement gate flow for better gate stack control. Problem The top challenges of Vertical Field Effect Transistors (VFET) are achieving a bottom spacer formation with uniform thickness and a low-k value and the formation of high-k metal gate (HKMG) after source drain (S/D) formation. Solution/Novel Contribution This solution introduces a novel flow to improve the thickness control of the bottom spacer with a lower k-value. In addition, it provides full replacement gate flow for better gate stack control. Method/Process The following figures represent the process flow of the solution. Figure 1: After VTFE FIN formation, conformal SiGe dep (or other sacrificial material like room temp Al2O3)

Figure 2: After HDP oxide formation (this is to define gate length)

Figure 3: Top SiGe or Al2O3 removal

Figure 4: Additional SiN spacer formation

Figure 5: (Optional) Additional top S/D formation

Figure 6: Oxide RIE, selective to SiN

Figure 7: SiGe or Al2O3 etch

Figure 8: Selective SiGe or Al2O3 isotropic etch back

Figure 9: Option 1:

Figure 10: Key benefits and unique structure for Option 1

Figure 11: Option 2

Figure 12: Key benefits and unique structure for Option 2