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Method and Structure of forming Vertical CMOS device with MIM capacitor

IP.com Disclosure Number: IPCOM000253192D
Publication Date: 2018-Mar-13
Document File: 6 page(s) / 187K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for integrating a metal-insulator-metal (MIM) capacitor with a vertical complimentary metal-oxide-semiconductor (CMOS) device using the current vertical field effect transistor (VFET) integration process flow, with minimum manufacturing cost. The novel solution is a method and structure for forming a vertical CMOS device and two plate MIM capacitors on the same chip.

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Title Method and Structure of forming Vertical CMOS device with MIM capacitor Abstract Disclosed is a method for integrating a metal-insulator-metal (MIM) capacitor with a vertical complimentary metal-oxide-semiconductor (CMOS) device using the current vertical field effect transistor (VFET) integration process flow, with minimum manufacturing cost. The novel solution is a method and structure for forming a vertical CMOS device and two plate MIM capacitors on the same chip. Problem Vertical metal-oxide-semiconductor field effect transistors (MOSFETs) have been explored as a viable device option for continued complimentary metal-oxide- semiconductor (CMOS) scaling beyond 7nm node. Metal-insulator-metal (MIM) capacitors are often used in integrated circuits as decoupling capacitors for microprocessor units (MPUs), radio frequency (RF) capacitors in high frequency circuits, and filter and analog capacitors in mixed-signal products. A method is needed for integrating an MIM capacitor with a vertical CMOS device using the current vertical field effect transistor (VFET) integration process flow, with minimum manufacturing cost. Solution/Novel Contribution The novel solution is a method and structure for forming a vertical CMOS device and two plate MIM capacitors on the same chip. Only one additional mask is required, using the current VFET process on record (POR) integration process. Figure 1: Three plate MIM capacitor integrated with a CMOS vertical transistor on the same chip

Method/Process

1. Start with a semiconductor substrate (e.g., bulk Si substrate) 2. Form fins nFET, pFET, and MIM capacitor region 3. Form isolations (e.g., shallow trench isolation (STI))

Figure 2: Steps 1-3

4. Form sacrificial spacer (nitride or...