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Smart System to prepare Fab Route build from Design

IP.com Disclosure Number: IPCOM000253193D
Publication Date: 2018-Mar-13
Document File: 6 page(s) / 91K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a process improvement for semiconductor manufacturing fabrication (fab). The new graphical-based method provides a direct means to derive a device list from the submitted graphical data. Validation of the pre-order mask set and devices against the designers' graphical database assist in building a robust route for downstream manufacturing in fabs.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 38% of the total text.

Title Smart System to prepare Fab Route build from Design Abstract Disclosed is a process improvement for semiconductor manufacturing fabrication (fab). The new graphical-based method provides a direct means to derive a device list from the submitted graphical data. Validation of the pre-order mask set and devices against the designers’ graphical database assist in building a robust route for downstream manufacturing in fabs. Problem The manual process of gathering required details needed before semiconductor manufacturing fabrication (fab) takes two weeks to complete. Missing information can incur additional delays in confirming the details from the customer. Visual review and verification is prone to human errors. In addition, no automated process is available that lists information on a third-party IP, which is required for determining royalty payments. The current method relies on design teams to run logic to physical checking and provide a device list to manufacturing. If designers change device content after providing a device list, manufacturing has no way to detect the change and mask sets; manufacturing process routings are not correctly set up, resulting in scrap and schedule impact. Solution/Novel Contribution The novel contribution is a smart system to prepare a fab route build from design. The solution is a graphical-based method that provides a direct means to derive a device list from the submitted graphical data. Validation of the pre-order mask set and devices against the designers’ graphical database assist in building a robust route for downstream manufacturing in fabs. Method/Process The process uses the design manual (DM) files and PDKs to create input files for the Validator. From that, the process creates Feature Seed Statements and Boolean equations to extract the features. The process then loads the customers design data and creates a layer database (DB). The validator performs device recognition, referred to as extraction. Once a single existence of a feature/device is validated, the code moves on to the next seed in the list (unlike LVS/DRC, which must identify all the feature/devices). The validator only cares about the required masks, so identifying one of each seed is adequate. The validator collects all the information from the DB to:

1. Perform layer checks 2. Identify required masks3. Identify devices found4. Determine the metal stack from the layers found5. Calculate die size

The Validator then generates a PDF report, route instructions, and extensible markup language (xml) for downstream tools.

The graphical-based device list derivation method to determine the mask list and process list for semiconductor manufacturing follows these steps:

1. Define device graphical construct for each device type allowed in technology 2. Create Graphical Database, where masks and process steps used in

technology are related to device graphical constructs 3. Check product graphic data for each device graphical construct in...