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Inner Spacer formation using a Deposition-Etch technique for Beyond-7nm Nanosheet CPP scaling

IP.com Disclosure Number: IPCOM000253603D
Publication Date: 2018-Apr-16
Document File: 7 page(s) / 196K

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The IP.com Prior Art Database

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Inner Spacer formation using a Deposition-Etch technique for Beyond-7nm Nanosheet CPP scaling

Disclosed is a mechanism for forming an inner space formation using a deposition-etch technique for beyond 7nm nanosheet CPP scaling. The mechanism includes an integration flow for Nanosheet-FET Inner spacers compatible with CPP scaling beyond 48CPP. Inner Spacers that meet structural and electrical requirements are formed while minimizing the lateral space consumption to minimize the risk of pinch-off between the gates.

In an embodiment, formation of Inner spacers is carried out using a Deposition-Isotropic Etch technique. Figures 1 through 9 illustrates the steps.

After PC, Spacer formation

Figure 1

After NS FIN recess, and SiGe indentation

Figure 2

Inner Spacer – 1st Thin SiN liner dep (Thickness=Target thickness/2)

Figure 3

OPL fill and CMP

Figure 4

OPL directional RIE

Figure 5

Isotropic 1st Thin SiN liner removal (e.g. Wet, AMAT frontier or TEL Certas)

Figure 6 OPL Strip

Figure 7

Inner Spacer – 2nd Thin SiN liner dep (Thickness=Target thickness/2)

Figure 8

Isotropic 2nd Thin SiN liner removal (e.g. Wet, AMAT frontier or TEL Certas)

Figure 9

In another embodiment, formation of inner spacers is carried out using a Deposition- Anisotropic Etch technique. Figure 10 through 14 illustrates various steps.

After PC, Spacer formation

Figure 10

After NS FIN recess, and SiGe indentation

Figure 11

Directional RIE 1st Thin SiN liner

Figure 12

Inner Spacer – 2nd Thin SiN liner dep (Thickness...