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Work Around Mechanism Via Debug-Marked Bits in Completion Table for Microprocessor

IP.com Disclosure Number: IPCOM000253938D
Publication Date: 2018-May-16
Document File: 2 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

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Work Around Mechanism Via Debug-Marked Bits in Completion Table for Microprocessor

In processor design, each instruction can be marked for debug handling, working around hardware, or software issues.

The novel contribution is a workaround mechanism via debug-marked bits in a completion table for a microprocessor.

The Instruction Completion Table (ICT) has one debug mark per instruction (i.e., per entry), which can be set either at dispatch or by the execution unit on-the-fly during execution, when the execution unit needs the processor to perform special services such as flushing it out (next-to-complete (NTC) flush) or flushing the next youngest instruction (NTC+1 flush). The debug mark can also perform a workaround to flush out other threads to give its own thread more resources.

The debug-marked bit can be set by three different mechanisms, described here.

1. ICT Process to support debug marked by Instruction Fetch Unit (IFU): A. The IFU performs instruction matching and sets the debug marked bit = 1

before sending the instruction to Instruction Sequencing Unit (ISU) B. At ISU Dispatch, the system sends the instruction to the ICT C. The ICT writes the debug marked bit into the ICT for dispatching

instructions D. The debug marked instruction finishes executing and sends the finish

instruction TAG (ITAG) to the ICT E. The ICT sets the finish bit = 1, but the active Debug Marked bit gates-off

the ready-to-compete (RTC) bit F. When the Debug Marked instruction reaches next to complete (NTC), the

exception logic takes over to examine the various special actions that it needs to perform when it encounters a Debug Marked instruction. The actions can be:

i. flush NTC ii.flush NTC+1 or, iii. flush the other threads

G. Following the ITC’s performance of the special handling steps (i.e., flush NTC, flush NTC+ etc.), it sends a signal to the ICT to set the RTC bit of the Debug Marked instruction to allow it to complete

2. ICT Process to support debug marked Work Around Trigger (WAT): A. Various workaround triggers (WAT) in the core can send a request to ISU

to mark instructions for a duration. For instance, if the (WAT) detects some events in the core, it can mark instructions for a number of cycles to work around some hardware issu...