Integration of ESD Structures in Vertical Gate FINFET Process

Title Integration of ESD Structures in Vertical Gate FINFET Process Abstract Disclosed is a method for integrating electrostatic discharge (ESD)/passive devices into vertical gate FIN and planar (non-FIN) regions of a vertical-gate fin Field Effect Transistor (FINFET) process. Problem A system or method is needed for the integration of electrostatic discharge (ESD)/passive structures into a vertical gate fin Field Effect Transistor (FINFET) process. Solution/Novel Contribution The novel contribution is a method for integrating ESD/passive devices into vertical gate FIN and planar (non-FIN) regions of a vertical-gate FINFET process. Method/Process The novel method comprises:

1. A field plate over an insulating layer configured: a. Vertical portion around the fin region b. Horizontal portion over the planar (non-fin) region

2. P+ and N+ region formed in vertical FIN composed of epitaxial Si 3. P+ and N+ formed in planar (non-FIN) regions composed of either epitaxial Si or

diffusion implantation Figure 1: Solution: Vertical Fin based ESD SCR

Figure 2: Embodiment #1 – ESD Gated Diode

Figure 3: Embodiment #2 – ESD FET with ballast resistor

The following figures illustrate the implementation of the method.

Figure 4: Process flow

Figure 5: Process flow – Post FIN; Deposit mask/nitride

Figure 6: Deposit photo-resist (PR)

Figure 7: Open PR for gate processing

Figure 8: Etch nitride

Figure 9: Deposit gate material

Figure 10: Open region for S/D implantation

Figure 11: Source/Drain imp...