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Integration of ESD Structures in Vertical Gate FINFET Process

IP.com Disclosure Number: IPCOM000255036D
Publication Date: 2018-Aug-27

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for integrating electrostatic discharge (ESD)/passive devices into vertical gate FIN and planar (non-FIN) regions of a vertical-gate fin Field Effect Transistor (FINFET) process.