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Programmable Test Pattern Generator and Controller

IP.com Disclosure Number: IPCOM000255318D
Publication Date: 2018-Sep-17

Publishing Venue

The IP.com Prior Art Database

Abstract

Memories are typically tested using preset test patterns that exercise the memory core. In the case of embedded memories, e.g., where memory is integrated within an application-specific integrated circuit (ASIC), conventional testing is not effective in uncovering defects in the memory-ASIC interface. Stress conditions, e.g., excessive bus activity, saturated interface bandwidth, power surges, noise, etc., that arise in operation are not reproduced adequately in the test phase. Memory defects that manifest under specific conditions, e.g., after many cycles of memory access, under certain data/address sequences, when neighboring memory cells hold particular values, etc., are often not uncovered. This disclosure describes a compact, programmable, built-in test unit capable of generating arbitrary sequences of memory accesses and read/write operations, pattern-loops, address-jumps, etc. The embedded memory receives test patterns from the test unit in a manner that mimics memory accesses from the ASIC. Both memory core and interface are subjected to stress or corner conditions as experienced in operation. Programmability of the test unit enables trapping of conditions that surface rarely-manifested defects. KEYWORDS ASIC testing; memory testing; ATPG; test pattern generation; MBIST; built-in self-test; highbandwidth memory (HBM); DRAM; design-for-test; embedded memory;