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Process for Forming CMOS Airgap Spacer Via Contact Liner Etch

IP.com Disclosure Number: IPCOM000255777D
Publication Date: 2018-Oct-12
Document File: 2 page(s) / 33K

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The IP.com Prior Art Database

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Process for Forming CMOS Airgap Spacer Via Contact Liner Etch In order to reduce Ceff, low-K material is used for CMOS spacer. Air provide lower K than typical low-K materials. By forming airgap spacer, device performance is enhanced. Existing fabrication process form air gap by completely removing spacer. However, it damages the metal gate and introduce moisture and change WF. There is therefore a need for a process for reducing exposing metal gap to air but still maintain the airgap in spacer area. Disclosed is a fabrication process for forming air gap spacer is using contact metallization process. Following figures illustrates the steps for forming air gap spacer in accordance with the fabrication process disclosed herein. Figure 1 illustrates the step of performing post-contact patterning wherein a sacrificial liner is deposited and bottom is etched.

Figure 1

As a next step, contact metallization and CMP is performed as shown in figure 2.

Figure 2

Moving, the process involves wet etch removal of sacrificial layer selective to MOL Low- K ILD and contact metal, for example dHF. This is shown in figure 3.

Figure 3

Thereafter, nitride spacer is removed laterally for forming airgap using DHF, COR or SiCoNi while keeping the Gate electrode intact as shown in figure 4.

Figure 4