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Low Contact Resistance Top S/D for VTFET Disclosure Number: IPCOM000255779D
Publication Date: 2018-Oct-12
Document File: 6 page(s) / 297K

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TITLE: Low Contact Resistance Top S/D for VTFET *Enter a brief abstract for this article

Disclosed is a method to combine a hot implant with Solid Phase Epitaxy

(SPE) to address bridging issues due to epitaxy overgrowth (i.e.,


*Enter the body of your Invention Disclosure Publication below. You may include drawings and highlighting as appropriate. The problem addressed herein is with top source drain (SD) formed by trench epitaxy (epi). To form a typical 20 nm thick top SD, the trench epi mushrooms over the space between fins. Without a deep trench to confine epi mushrooms, the epi overgrows on the dielectrics between fins. This leads to bridging issues. Silicon Nitride (SiN) hardmask (HM) on top of veridical fin sometimes is difficult to remove on the whole wafer, thus causing a no-epi problem. Solid Phase Epitaxy (SPE) is known to reduce conduce resistance. An SPE process will save one Extreme Ultraviolet (EUV) mask compared to a trench epi process. The solutoin is a method to combine a hot implant with SPE (hot implant + SPE). In the following process flow, steps 2-10 represent the novel contribution.

1. Incoming (fin h ≈ 40~60 nm, pending on SPE thk) 2. SiN (ESL) + TiOx hard mask deposition (depo) 3. EN litho / HMO / fin HM removal 4. Negative Field Effect Transistor (NFET) top SD junction by hot implant (plasma

doping) 5. Poly Amorphization Implantation (PAI) & NFET-SPE 6. SiN (p-liner) + TiOx liner depo 7. EP litho / HMO / fin HM removal + TiOx strip 8. Posi...