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Introduction of Dual Channel Strain in nanosheet CMOS

IP.com Disclosure Number: IPCOM000256176D
Publication Date: 2018-Nov-08
Document File: 5 page(s) / 87K

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The IP.com Prior Art Database

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Introduction of Dual Channel Strain in nanosheet CMOS Disclosed is a method providing a fabrication process for realizing channel strain in nanosheet transistor with Ge-rich SiGe encapsulation layer for both nFETs and pFETs. The typical Si nanosheet thickness should be around or smaller than 5nm to have the full volume inversion operation. In such situation, carriers conduct full in partially tensile strained Si with boosted mobility and be free of interface roughness scattering. The typical SiGe capping layer is around 2nm, which is partially compressive strained by Si. Due to the quantum well in valence band side of SiGe to Si hetero-junctions, holes mainly conduct in SiGe layer with boosted mobility from compressive strain. The following figures illustrate various fabrication steps in accordance with the method disclosed herein. The method starts from wafer with stacked SiGe/Si layers as shown in figure 1.

Figure 1

At the next step, the method forms PC/Spacer and forms inner spacer and Source/Drain epi. The resulting structure is shown in figure 2.

Figure 2

Moving on, the method performs oxide deposition and CMP as illustrated in figure 3.

Figure 3

Subsequently, the method performs polly pull to get the structure as shown in figure 4.

Figure 4

Thereafter, nanosheet is released with the high SiGe layer removed as illustrated in figure 5.

Figure 5

Subsequently, the method performs ALD GeOx deposition. The resulting structure is shown in figure 6.

Figure 6

Then, the method p...