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Dynamically extending the hardware Performance Monitoring Unit (PMU) events using uncore engine.

IP.com Disclosure Number: IPCOM000257035D
Publication Date: 2019-Jan-12
Document File: 5 page(s) / 963K

Publishing Venue

The IP.com Prior Art Database

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Dynamically extending the hardware Performance Monitoring Unit (PMU) events using uncore engine

Abstract - Disclosed is a method for dynamically creating a new hardware pmu event for per- CPU or nest unit. Dynamic event can then be consumed by application in-band for resource monitoring or application tuning.

Disclosed is a method for adding dynamic event in the system without adding any new hardware logic to processor and without re-programming any hardware logic in the processor. Dynamic event added does not use any core cpu cycles to implement new hardware pmu event. Any number of dynamic pmu events can be added with proposed approach.

Background - Resource monitoring is important requirement in today's computer architecture because of complex computing environment and in enterprise cloud offering too. Workloads of different criteria will be run and monitoring the system resources to alert any threat or over usage of resources like memory is important, this can be achieved by making use of Performance Monitoring Units in the hardware. There are counters defined specifically for obtaining information related to memory, temperature etc. In-case of situations where user likes to be notified about a custom defined threshold, routines/applications can be written to manipulate these counter values at specified intervals of time, but those solutions uses the CPU cycles. Leveraging uncore engines in Power systems to get metering information related to memory, CPU and other resources utilization can be cost effective solution. The solution covered in this article will allow to execute custom programs from user in the uncore engine and thereby extend the CPU hardware events. Existing studies found in this area with keywords - coprocessor, uncore engine, dynamic events, pmu are listed below: 1. US7490117 talks about dynamic performance monitoring based approach in memory management. It also mentions the use of pmu events like cache miss and cache hits to understand the memory usage and thereby efficiently optimize memory usage. And hence this is not exactly related to our solution in this article. 2. US6898718 talks more about the generic PMU and events in the hardware, but these units are fixed in the silicon and events can not be extended at runtime. This article propose a solution to dynamically extend the hardware performance monitoring events with zero overhead on Core cycles using uncore engines. Summary - Most processors has on-chip performance monitoring hardware to monitor micro architectural events like cache miss, branch miss, cpu cycles, memory bandwidth etc. They support limited set of events to look at specific type of events. But there are cases (like in Cloud offering) where multiple of these hardware events needs to be monitored to understand resource usage of the system. There are existing products/solutions for performance monitoring in various processors like Power, Intel, ARM. Intel's System On Chip has new set of uncore performa...