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Control of BIST voltage level 1

IP.com Disclosure Number: IPCOM000258307D
Publication Date: 2019-Apr-29

Publishing Venue

The IP.com Prior Art Database

Abstract

A system for controlling the operating voltage of the SoC during Self-Test. Normally this Self-Test is implemented solely on the SoC and is referred to as Built In Self-test (BIST), however the test may also be carried out by a separate device. For the purposes of this publication, the self-test shall be referred to as BIST. The SoC communicates with the external PMIC or Internal SoC power supply to modify the operating voltage of the device used during BIST testing to be different from the normal operating voltage of the SoC. This allows new use cases for the BIST such as: 1)Earlier detection of defects. 2)Possibility to attempt repair of SoC by repetitive BIST testing at different voltages, giving increased availability. 3)Improvement of SoC lifespan by identifying voltage levels where BIST tests fails, and then moving the SoC supply to operate the SoC within the new optimum voltage supply window. 4) Improvement of SoC availability by identifying the voltage levels where BIST tests fails, and then moving the external voltage supply to operate the SoC within the new functioning voltage supply window for a limited period of time to enable the vehicle to operate until it reaches a destination.