Month of January 2006 - Page Number 10

Showing 91 - 100 of 395 from January 2006
Browse Prior Art Database
  1. 91.
    Disclosed is a method for SDL non-destructive parking that increases the usage of domino parking as a means of leakage power saving in microprocessor circuit design. Benefits include minimizing speed degradation, minimizing the increase of total transistor width due to SDL parking, and also reducing SDL leakage power...
    IPCOM000133378D | 2006-Jan-25
  2. 92.
    Disclosed is a method for a circuit and algorithm that calibrates the thermal sensor at any temperature, using only Sort (-25oC) and Class (100oC) measurements. Benefits include enabling the digital thermal sensor to achieve its specified performance.
    IPCOM000133377D | 2006-Jan-25
  3. 93.
    Disclosed is a method that uses a new tuning technique that achieves a lower supply noise sensitivity and a wider tuning range, compared to current state of the art techniques. Benefits include attaining a greater power supply noise rejection (PSRR).
    IPCOM000133376D | 2006-Jan-25
  4. 94.
    Disclosed is a method for a multi-core CPU with multiple phase locked loops (PLL) and multiple clock domains. The disclosed method uses a special scheme to synchronize the clock in each clock domain. Benefits include allowing two buses to operate at odd ratios, while eliminating any uncertainties between them.
    IPCOM000133375D | 2006-Jan-25
  5. 95.
    Disclosed is a method for a symmetrical bias (SB) differential amplifier that increases the difference between the inputs, while maintaining the common mode of the input. Benefits include high gain and consistent performance across all common modes.
    IPCOM000133374D | 2006-Jan-25
  6. 96.
    Disclosed is a method that allows a microprocessor to verify that the platform it is installed in complies with the manufacturer’s specifications for power delivery quality.
    IPCOM000133373D | 2006-Jan-25
  7. 97.
    Disclosed is a method that uses globally or locally defined values to conditionally remove graphical logic from a design; the logic gates are removed based on a user-defined numeric expression. Benefits include creating various silicon designs derived from the same design database.
    IPCOM000133372D | 2006-Jan-25
  8. 98.
    Disclosed is a method that uses a clock gating design to provide dynamic switching between the active and standby states of the unused and idle logic blocks. Benefits include reducing overall power consumption.
    IPCOM000133371D | 2006-Jan-25
  9. 99.
    Disclosed is a method that improves DLL bandwidth by using a different pattern for the reference clock, while protecting the DLL from false lock situations. Benefits include reducing the rejection to substrate and supply noise.
    IPCOM000133370D | 2006-Jan-25
  10. 100.
    Disclosed is a method for a dynamic offset cancellation circuit that cancels any input-referred offset in the amplifier due to component mismatch (i.e. threshold voltage) or serial link performance. Benefits include improving the input sensitivity of the receiver.
    IPCOM000133369D | 2006-Jan-25