Month of December 2011 - Page Number 9

Showing 81 - 90 of 437 from December 2011
Browse Prior Art Database
  1. 81.
    This invention presents the method and structure to form one side buried strap for memory cell on SOI. This invention is using self-alignment scheme. It has simple and cost effective process (several processes are skipped, including poly II fille/recess II, strap RIE) and Easy STI fill and possibility of metal (TiN)...
    IPCOM000213581D | 2011-Dec-21
  2. 82.
    Disclosed is a method to create quantized effective width by introducing Semiconductor on Insulator (SOI) substrate with different active device thickness.
    IPCOM000213580D | 2011-Dec-21
  3. 83.
    A method and system for tuning device widths in a finFET device is disclosed. The method and system provides a controlled fin capping process precisely creating thick gate dielectric cap.
    IPCOM000213579D | 2011-Dec-21
  4. 84.
    A method of creating a diffraction grating of tight pitch through guided self-assembly is disclosed.
    IPCOM000213578D | 2011-Dec-21
  5. 85.
    SOI technologies must offer a top-side substrate contact, such as IBM's BI contact. The BI process involves a poly plug. Our invention is a simplified "BI" contact using an e-SiGe S/D formation step, such as would be found in a typical ETSOI or FinFET process flow.
    IPCOM000213577D | 2011-Dec-21
  6. 86.
    A method for measuring depth, profile and critical dimensions of Through-Silicon-Via (TSV) is disclosed. The method further includes cleaning the TSV by forming a reverse structure of the TSV on the entire wafer coating and subsequently removing the reverse structure of the TSV.
    IPCOM000213576D | 2011-Dec-21
  7. 87.
    A method for epitaxial growth on Si is disclosed. Here, an epitaxy (Epi) channel such as tensile strained Si and compressively strained SiGe is grown on FET active regions.
    IPCOM000213575D | 2011-Dec-21
  8. 88.
    A method and system for determining health of semiconductor wafers during production is disclosed.
    IPCOM000213574D | 2011-Dec-21
  9. 89.
    Disclosed is a method to produce optimal electrical and thermal conductivity of the post on which a specimen is mounted for Atom Probe Tomography (APT), thus allowing for a more reliable analysis. The method entails siliciding the currently available coupon that is used as the specimen holder.
    IPCOM000213573D | 2011-Dec-21
  10. 90.
    IPCOM000213572D | 2011-Dec-21