Month of March 2014 - Page Number 18

Showing 171 - 180 of 476 from March 2014
Browse Prior Art Database
  1. 171.
    Disclosed is a damascene dummy gate process for fabricating Replacement Metal Gate (RMG) fin Field Effect Transistor (finFET) devices, where a new sacrificial dummy gate material is introduced, which can be SiN in one embodiment. The process uses a damascene trench for a dummy gate formation patterned selectively...
    IPCOM000235786D | 2014-Mar-25
  2. 172.
    Disclosed is a method to form FinField Effect Transistors (FinFET) without fin damage. The novel approach is to deposit the spacer dielectric with a thickness greater than the target spacer thickness, anisotropically etched to expose the top of the fin. Ultimately, the new process makes it possible to remove the...
    IPCOM000235785D | 2014-Mar-25
  3. 173.
    Disclosed are a method and structure that enable the extension of a fin merge scheme to future nodes.
    IPCOM000235784D | 2014-Mar-25
  4. 174.
    Disclosed is a method for growing a thin film with a faster growth rate at the bottom of smaller holes/trenches compared to wide flat areas or larger holes/trenches. This method accommodates different design structures with various critical dimensions.
    IPCOM000235783D | 2014-Mar-25
  5. 175.
    A method and system is disclosed for monitoring work in progress (WIP) using a real time database. The disclosed method and system monitors WIP more efficiently by creating real time and customizable central database that continuously gets updated and provide real time WIP data.
    IPCOM000235782D | 2014-Mar-25
  6. 176.
    A method and system is disclosed for suppressing bulk punch through leakage in bulk FinFET. The method and system creates a structure using a dielectric that is inserted at the bottom of the source/drain regions. The structure creates a physical barrier which limits the source/drain dopants from being so deep...
    IPCOM000235781D | 2014-Mar-25
  7. 177.
    Disclosed is a method to use multiple sacrificial Siege layers sandwiched between n+ silicon layers (or SiGe with lower percentage of Ge) to form arbitrary dielectric isolation thickness for a bulk Fin Field Effect Transistor (FinFET). The lower percentage of Ge regions act as a buffer to the higher percentage of...
    IPCOM000235780D | 2014-Mar-25
  8. 178.
    Disclosed is a cleaning device for removal of unwanted ceramic debris generated during the process of laminate sizing. The cleaning device automatically adjusts to thickness of different parts, thereby efficiently cleaning the ceramic debris.
    IPCOM000235779D | 2014-Mar-25
  9. 179.
    A method and system is disclosed for analysing and improving performance of operators. The method and system provides a measurement tool that analyses performance of one or more operators and aids in evaluation and improvement of performance of the one or more operators.
    IPCOM000235778D | 2014-Mar-25
  10. 180.
    Disclosed is a methodology to establish a link between time-dependent dielectric breakdown (TDDB) information and spatial context in spatial wafer maps.
    IPCOM000235777D | 2014-Mar-25