Month of March 2014 - Page Number 19

Showing 181 - 190 of 476 from March 2014
Browse Prior Art Database
  1. 181.
    Disclosed are a method and system to detect a process window shift within wafers that may cause fail patterns in a functional test or a performance test. The methods detect predefined fail patterns using data mining methods and exclude faked signals of match.
    IPCOM000235776D | 2014-Mar-25
  2. 182.
    Disclosed is an approach for a via level airgap interconnect. The method is to replace the dielectrics at via levels with air (k1), in order to greatly reduce interlevel capacitance. The approach also uses refractory metal in the via to improve reliability.
    IPCOM000235775D | 2014-Mar-25
  3. 183.
    A method and system is disclosed for providing a metal gate stack comprising a combination of metals and a graphene liner material existing preferentially between the metal gate stack and surrounding insulator materials such as, but not limited to, gate dielectric layers and sidewall spacers.
    IPCOM000235774D | 2014-Mar-25
  4. 184.
    A method is disclosed for forming one or more n-channel Field Effect Transistor (nFET) junctions using an in-situ co-doped epitaxy of arsenic and phosphorus for merging nFET fins.
    IPCOM000235773D | 2014-Mar-25
  5. 185.
    Disclosed are a system and method for performing static timing analysis of digital integrated circuit wherein timing constraints for at least one first timing point are dependent on computed timing data for at least one second timing point. The second timing point is upstream of the first timing point. Callbacks...
    IPCOM000235772D | 2014-Mar-25
  6. 186.
    Disclosed is a method to combine the advantages of both the bulk and Semiconductor on Insulator (SOI) approaches to multiple fin heights in order to economically form Fin Field Effect Transistors (FinFETs) of variable fin height (Hfin).
    IPCOM000235771D | 2014-Mar-25
  7. 187.
    A method and system is disclosed for utilizing titanium oxygen getter and optimized stoichiometry Titanium Nitride (TiN) barrier for preventing contact profile distortion and hollow CA.
    IPCOM000235770D | 2014-Mar-25
  8. 188.
    A method is disclosed for optimizing corner rounding and connectivity for inner vertices by stitching designs to reduce a corner rounding radius (CRR), increasing an overlapping area, increasing the minimum pitching width and improving the line end pattern fidelity.
    IPCOM000235769D | 2014-Mar-25
  9. 189.
    A method is disclosed for integrating dual-epitaxy with equivalent junction overlap. The method includes undercutting Source/Drain (S/D) region in a device polarity to compensate for a difference in spacer thickness.
    IPCOM000235768D | 2014-Mar-25
  10. 190.
    Disclosed is a method to generate a list of special pattern layout within a chiplet/TEG and output the results into a spreadsheet.
    IPCOM000235767D | 2014-Mar-25