Month of December 2014 - Page Number 1

Showing 1 - 10 of 332 from December 2014
Browse Prior Art Database
  1. 1.
    IPCOM000240099D | 2014-Dec-31
  2. 2.
    The invention relates to fittings that are attachable to thin wall structures for use with high pressure pneumatic and hydraulic systems in aircraft.
    IPCOM000240098D | 2014-Dec-30
  3. 3.
    A novel immature embryo based method for high efficiency transformation of indica rice with glyphosate-N-acetyltransferase (GLYAT) genes to produce glyphosate tolerant indica rice lines achieved about 70% single copy events and a transformation efficiency of approximately 30 - 50%.
    IPCOM000240097D | 2014-Dec-30
  4. 4.
    Neuartiger Isolierrohstoff
    IPCOM000240096D | 2014-Dec-30
  5. 5.
    Disclosed is a method to make a stacked die assembly using an integrated protective coating
    IPCOM000240095D | 2014-Dec-30
  6. 6.
    A method and apparatus is disclosed for detecting Copper (Cu) contamination of semiconductor interconnects and vias. The Cu contamination is defined if one or more parameters shift threshold such as, but not limited to, resistance shift, transistor on current shift, transistor threshold voltage shift, leakage current...
    IPCOM000240094D | 2014-Dec-30
  7. 7.
    Disclosed is a method and system for providing an automated response by using a dynamic knowledge base to augment a static knowledge base. The method and system relies on heuristics to automatically draft a response for a user query.
    IPCOM000240093D | 2014-Dec-30
  8. 8.
    Disclosed is an integrated circuit with dummy metal fillers and interconnect routing and a method for forming heat sinks by adding the dummy metal fillers and interconnect routing.
    IPCOM000240092D | 2014-Dec-30
  9. 9.
    Disclosed is a method to account for the activity factor of clock nets and data nets during parasitic extraction to determine the effective frequency of the signal, thereby reducing pessimism in parasitic extraction.
    IPCOM000240091D | 2014-Dec-30
  10. 10.
    Disclosed is a method of timing integrated circuits for optimization in order to reduce performance sensitivity of standard cell(s) in timing paths. In addition, the approach for placement perturbation to reduce leakage power is novel.
    IPCOM000240090D | 2014-Dec-30