Month of September 2018 - Page Number 7

Showing 61 - 70 of 388 from September 2018
Browse Prior Art Database
  1. 61.
    IPCOM000255468D | 2018-Sep-27
  2. 62.
    IPCOM000255467D | 2018-Sep-27
  3. 63.
    IPCOM000255466D | 2018-Sep-27
  4. 64.
    Disclosed is a method to reduce the contact resistance between two interconnect levels in advanced nodes by utilizing an anisotropic liner formation along the via sidewalls to minimize the liner material at the interface between the via and the underlying line.
    IPCOM000255465D | 2018-Sep-27
  5. 65.
    Disclosed are a method and structure for an inner spacer process to modulate the threshold voltage (Vt) and reduce parasitic capacitance in a multi-threshold Vt scheme. The core idea is for an integration scheme of a Field Effect Transistor (FET) with a spacer refill process to simultaneously achieve multi-Vt and form...
    IPCOM000255464D | 2018-Sep-27
  6. 66.
    IPCOM000255463D | 2018-Sep-27
  7. 67.
    Disclosed are a source/drain last, metallic source/drain structure and a method for its formation that uses source glass source films.
    IPCOM000255462D | 2018-Sep-27
  8. 68.
    IPCOM000255461D | 2018-Sep-27
  9. 69.
    Disclosed are a method and structure for forming nanosheet devices with low gate contact resistance using a pair of channel group sheets.
    IPCOM000255460D | 2018-Sep-27
  10. 70.
    Disclosed is a new mechanical polish (CMP) system comprising multiple modules. One module for polishing a substrate. Another is an etch module, adjacent to the CMP module, for performing an etch process. Another is an etch module configured to hold a CMP head. The solution also includes a means for transporting a...
    IPCOM000255459D | 2018-Sep-27